Senior Verification engineer in a growing team responsible for pre-Silicon ASIC Verification of complex chips, implementing G.fast protocol.
As part of the role, you will architect, develop & own blocks / sub-chip / system-level verification benches.
You will be a major contributor to advanced SV UVM methodologies and to infrastructure development.
You will be of advanced DV flow, using state of the art development & Verification tools.
Must have 8+ years of experience in metric-driven ASIC verification
Must have extensive experience in SV/Specman using UVM methodology
Must have experience in both unit-level, as well as sub-system/full-chip verification
Must have BSc in EE / CS from well-known University
Experience in scripting & automation languages (Python, Perl, TCL) - Advantage
Experience in verification of networking blocks - Advantage
Working with Emulation - Advantage
Experience in Formal Verification - Advantage