משרות backend

B.Sc in Electrical Engineering - Mandatory. Experienced Backend engineer 2-8 years in Backend - Mandatory.

B.Sc in Electrical Engineering - Mandatory. Experienced Backend engineer 2-8 years in Backend - Mandatory.

" BSEE of known university (Technion ,BGU,TLU) " Proven experience with backend team management focused on TSMC backend flow on large chips. - Relevant only for the TL. " Proven knowledge and deep understanding and "hands on" of backend tools (cadence backend is advantage). - Must! Proven knowledge of timing aspects. - Must! Deep understanding and experience 40nm technology in details. Proven knowledge on power optimization on deep sub-micron processes. Experience with fast IOs (DDR) an

5 שנות נסיון נסיון ב- P&R בסביבת Timing ידע בפיזיקל וריפיקציה- יתרון. הכרות עם סביבת CADANCE Encounter - חובה Hands-on רקע בסקריפטים (TCL) - יתרון

הנדסאי/ת חשמל / אלקטרוניקה נסיון קודם במעבדה ניסיון בהפעלת ציוד לבדיקת רכיבים - יתרון (עדיפות לניסיון בתחום ההייטק). אנגלית ברמה טובה

BSc Electrical Engineering
Experience in the P&R flow for more than four years.
Did all stage of P&R (from floorplan to extraction).
Advantage experience in DFT for more than two years.
Background in Synthesis.
Advantage experience in design.
Advantage experience STA.

B.Sc in Electrical / Computer Engineering - Mandatory Courses on backend design tools -Optional Course in RTL Verilog coding. Experience in backend:STA/DFT implementation of ASIC/CPU - advantage - Knowledge in Verilog - advantage Knowledge of Synopsys backend tools - advantage

Minimum 7 years hands-on experience with advanced RTL to GDS IC design flow. Experience must include: 1. Synthesis. 2. Constraint writing. 3. Equivalent checking. 4. Floor-planning. 5. Clock Tree synthesis. 6. Static Timing Analysis. 7. Timing driven Place and Route. 8. Noise Analysis. 9. Power Analysis. 10. Low power design. Knowledge and understanding of VLSI design and environments (experience with Synopsys tools ) Experience with 65nm-45nm process would be a great advantage. E