Job Qualification:
BSc in Computer science/ Electrical engineering from known University-Must. Strong background in signal processing and/or communications protocols-Must. AT least 5yearsexperience as VLSI Design Eng with Verilog-Must. Experience with synthesis and STA-Must. Experienced in implementation of complex communication IP - Advantage. understanding of fix point implementation, modulation, coding, detection, equalization, timing/phase recovery - Advantage. Experienced in small geometry process nodes - Advantage. C++, SystemC - Advantage.
Position:
ASIC designer/VLSI
Location:
Tel Aviv - Center
Category:
Hardware
Job Capacity:
full time
Salary Range:
Avaliable for registered users only!
 
Job Description:
VLSI design engineer that will join the Design group Taking part in the architecture and implementation of complex: Wireless Networking IPsORphysical layer (PHY) transceiver channels Working closely with Ceragonsystem team developing together high end DSP and Networking IPs. Responsible for the correctness and timing closure of the IP Communicating, when require, with external vendor
Years of Experience:
Non Relevant
Company Occupation:
High Tech, Networking/datacom/telecom
Company Size:
Medium (50 - 150)
 
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