-10+ years of hands on with ASIC and FPGAs - Required;
-B.Sc. in EE (M.Sc. - Advantage) from TAU, Technion or Ber-Shiva universities (including grades average) - Required;
-Proven manager who Managed groups of over 10 engineers - Required;
-Ability to handle several project in parallel and manage cost, resources and requirements.
-Knowledge in Communication Physical Layer (Receiver, Transmitter …)- Required;
-Knowledge in Verilog and Matlab (C and C++ is an advantage). - Required;
Years of Experience: