Lead design, implementation, and verification of complex blocks, and or subsystems, of complex network processor IP.
-BSc in EE with minimum of 12 years of experience in similar roles
-Must have working knowledge, and skills in one or more of the following areas: SoC frontend design flow, synthesis flow, STA flow, DFT flow (advantage with Mentor TS), Spyglass EDA, CDC, DFT, LINT, LEC
-Excellent written and verbal communication skills
High Tech, Wireless, Networking/datacom/telecom