For a hi-tech company developing products in the field of digital communication, with offices in the Sharon
You will work on a full state of the art verification flow from architecture definition, through verification strategy, environment micro ARCH, test plan, functional coverage plans and up to advanced verification sign off process - combining the FV in state of the are multi-platform verification that fuse Functional Verification, Formal (using Jasper) and SW testing over Emulation.
Learn standard AMBA protocols as well as in-house protocol.
Create, simulate and debug FV TB and functional coverage.
Take ownership on Daily and Weekend based regressions to 100% pass rate over the course of the project, while daily tracking progress.
Collaborate with design, architecture and systems engineering teams to review specifications and architecture, extract features, and define verification plans accordingly.
Drive both functional and code coverage analysis to closure.
B.Sc /M.Sc. graduates in Electrical Engineering from a leading University.
At least 5+ Actual hands on experience in FV, using Jasper - advantage
Previous experience in managing teams of 2-4 is a plus.
Knowledge of SV is a must, SV-UVM, Specman and C++ is a plus.
Self-motivated and self-directed, proactive.
Ability to achieve results in a fast moving, agile flow and dynamic environment, both locally and across the organization.
Ability to troubleshoot and analyze complex problems.
Great communication skills, Team player.
High Tech, Semiconductor/capital equipment