Sr. Digital Verification Engineer

  • full time
  • 5+ years

Job Description:

Design and develop verification environment for state-of-the-art Flash solution IPs, working closely with Design and Algorithm engineers.
Leading the top-level IP verification effort from planning to delivery.
Plan the verification of complex digital design IP's by fully understanding the design specification and the implemented algorithms.
Working closely with architecture, design and algorithm teams to identify important verification scenarios.
Responsible for the full life cycle of verification, from verification planning to tests execution through IP environment building using System Verilog and UVM.
Define and establish new verification methodologies in the group.

Additional Positions:

Verification, Verification Engineer


Hybrid, Tel Aviv - Center



Job Qualifications:

" BSc. in Electrical Engineering/ Computer Science MSc. an advantage
" 5 years of hands on experience in VLSI verification
" Advanced knowledge of ASIC verification flows with System Verilog and UVM
" Experience in developing test benches from scratch
" Familiarity with scripting languages

Company Occupation:

Video/Audio Related, High Tech, Semiconductor/capital equipment

Company Size:

Large (150+)

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