The Verification Sensor team Is required to tackle the full flow of verification, from block & IP level to chip & system, including interfaces & deep understanding of all design flow and technical teams (such as Digital,Analog & FW).
We are looking for people with a broad set of technical skills, who are ready to tackle some of technology's greatest challenges, who have the ability to think out of the box and bring the disruptive technologies that will define our future.
What will you do?
" Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
" Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
" Create a constrained-random verification environment using SystemVerilog.
" Identify and write all types of coverage measures for stimulus and corner-cases.
" Debug tests with design engineers to deliver functionally correct design blocks.
" Collaborate closely with design and verification engineers in active projects and perform hands-on verification.
" Close coverage measures to identify verification holes and to show progress towards tape-out.
B.Sc. in Electrical Engineering; MSc. - an advantage
At least 4 years experience as verification engineer, completing at least 2 full chip development cycles
Knowledge in verification methodologies, tools (simulators and relative APIs, coverage tools, accelerators, formal, etc.), and techniques
Knowledge of Verilog or VHDL, System Verilog
Experience in C and Perl programming
Experience in building of verification environment from scratch, with the emphasis on verification methodology
Good knowledge of Unix environment and script languages
Methodological approach to building of verification environment and test plan
Methodological approach to the verification tasks planning and execution
Video/Audio Related, High Tech, Semiconductor/capital equipment
Medium (50 - 150)