For a hi-tech company developing chip's for communication devices, with offices in the center.
To join our talented team of experts in software development, validation and integration, digital signal processing, RF and digital chip design, hardware design and testing, and help us maintain and develop our leadership in the IoT/5G industry.
Will be responsible for the full flow on one of the sub systems in PHY or MAC from spec to design and verification and work with the P&R to close the HLB.
B.Sc. / higher in Electrical Engineering / Computer Engineering
At least 6 years of hands-on experience in one or more of the following ASIC area:
PHY / signal processing
MAC and Network
Programming language Verilog/System Verilog
Solid work experience involving synthesis & STA - an advantage
Experience with multi-clock domain designs - an advantage
Familiar with all front-end tools including lint, CDC and synthesis - an advantage
Good System understanding
Great communication skills
Open minded team player
High Tech, Semiconductor/capital equipment