Job Description:
- Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
- Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create a constrained-random verification environment using SystemVerilog.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Collaborate closely with design and verification engineers in active projects and perform hands-on verification.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
Location:
Hybrid, Tel Aviv - Center
Job Qualifications:
- BSc. in Electrical Engineering/ Computer Science MSc. an advantage
- 5 years of hands on experience in VLSI verification
- Advanced knowledge " BSc. in Electronic Engineering MSc. an advantage
- At least 3 years experience as verification engineer, completing at least 2 full development cycles
- Knowledge in verification methodologies, tools (simulators and relative APIs, coverage tools, accelerators, formal, etc.), and techniques
- Knowledge of Verilog or VHDL, System Verilog
- Good knowledge of Unix environment and script languages
- Methodological approach to building of verification environment and test plan
- Methodological approach to the verification tasks planning and execution
- Ability to work well in a team
Company Occupation:
Video/Audio Related, High Tech, Semiconductor/capital equipment
Company Size:
Large (150+)