Job Description:
For a hi-tech company developing satellite communication technologies, with offices in the Shefela / Haifa Matam area
Location:
Haifa area, Shfela area
Job Qualifications:
COT/ASIC physical design flow covering: Synthesis, Floorplanning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/pattern generation
Deep sub-micron (28nm or below) process technologies
Industry standard design processes for deep sub-micron designs
Problem-solving and analytical skills
Practical use of scripting languages Tcl/Python/Perl etc
Experience of at least one of the following EDA tool flows: Cadence or Synopsys
Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow
Managing/Interfacing to sub-contract design service providers
Education:
At least Bachelor of Science in Electrical Engineering, Computer Science, or related field from a major academic institute.
Company Occupation:
High Tech
Company Size:
Medium (50 - 150)