Senior Staff Design Verification Engineer

  • full time
  • 6+ years

Job Description:

The engineer will take ownership over a switch IP verification tasks, such unit level verification, cluster level verification. The engineer will work closely with designers and architects to understand the required functionality. He/She expected to take an active role, to influence the unit's architecture / micro architecture, to plan and implement the verification environment in SV/UVM, and to execute the verification plan until all quality criteria's are met.

Additional Positions:

Verification, Verification Engineer


Hybrid, Tel Aviv - Center



Job Qualifications:

B.E/B.Tech Electrical engineering from a known University.
M.E/M.Tech Electrical engineering an advantage.
Over 6 years of experience in digital verification.
Verification experience in SV, UVM and building verification environment from scratch is a must.
Knowledge of scripting languages, such as PERL, Python.
Design/RTL experience in Verilog or SV is an advantage.
Good learning , problem solving interpersonal and communication skills.
Ability to be a part of a team, working in cooperation
Knowledge of followings are an advantage:
- L2 / L3 / L4 Ethernet protocols knowledge
- Encryption / Authentication algorithms and protocols
- Precision Time Protocol (PTP, IEEE-1588)

Company Occupation:

High Tech, Semiconductor/capital equipment, Networking/datacom/telecom

Company Size:


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