Senior Layout Engineer

  • full time
  • 3+ years
  • Sharon area

Job Description:

For a branch of a large, multi-national company developing electronic components, with offices in the Sharon

To be primary responsibility for the analog layout, including floor plan and physical verification, of the company's semiconductor products and semiconductor IPs in the realms of image (CIS) and other sensors, which include sensing functions along with significant analog and digital processing

Additional Positions:




Job Qualifications:

At least 3 years experience in analog, mixed-signal IC layout and mask design for CMOS technologies

Extensive experience with CAD design tools and verification flows, using Cadence Virtuoso XL and Mentor Graphics Calibre (LVS/DRC)

Experience with post layout parasitic extraction tools (e.g., Calibre XRC)

Experience with analog layout methodologies and techniques to maximize component matching, improve noise immunity, and optimize parasitic layout

Experience programming with Cadence Skill, Calibre Standard Verification Rule Format and Perl

Knowledge of MS Office, specifically Excel and PowerPoint

Company Occupation:

High Tech

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