Job Description:
Technical responsibilities:
" Implement full P&R flow of Hierarchical level blocks & Top level from Netlist to GDSII:
" Place
" Clock tree synthesis
" Route
" STA, Sign-off
" Physical verification - DRC, LVS, ANT etc.
Job Qualifications:
" B.Sc in electrical engineering or higher.
" 5+ years of experience in Automatic Place & Route, Block level and Top
" Knowledge in writing scripts in TCL.
" Capable of working in a multi discipline / multi-site environment
Advantages
" Acquaintance with various aspects and considerations of place and route in full chip and block level flows from netlist to GDS: Floor plan, circuit, IR drop and EM prevention etc.
" Experience with Cadence P&R flow and tools
" Acquaintance with advanced nodes (16nm and below)
Company Occupation:
High Tech, Semiconductor/capital equipment