Job Description:
Design and implement complex FPGA-based systems for ultra low latency applications
Characterize system requirements and specs including SW-HW API
Debug production issues using systematic approach to narrow down problems to specific HW / SW domain
Characterize and implement HW debug and development infrastructures
Research optimal P&R strategies and implementation approaches to minimize latency without compromising on utilization and timing closure
Job Qualifications:
BSc/MSc in Electrical Engineering from a well known academic institute (Cum Laude).
At least 5 years experience in FPGA/VLSI development.
Proficient in HDL (Verilog / System Verilog / VHDL) language.
Familiar with all stages in FPGA build flow, including architecture, design, simulations, synthesis, place and route and timing closure.
Experience in hardware timing closure optimizations.
Lab debugging and troubleshooting skills.
Experience in FPGA development for Xilinx devices - advantage
Software skills in C/C++ - advantage.
" Scripting skills in Python / R / Tcl - advantage.
Self sufficient with a can-do attitude.
Team player with excellent communication skills.